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  1. Architectures …
 / Test 1

Test 1

Heterogeneous computing

  1. Moore’s law refers to: (7 points)

    • The doubling of the frequency in processors from time to time
    • The linear increase in the number of cores in a processor
    • The doubling of the number of transistors in processors from time to time
    • The increase in power generated by a processor from time to time

  2. The number of accesses per unit of time is called: (7 points)

    • Bandwidth
    • Computation cycles
    • Latency
    • Cache hit

  3. The idea of using memory hierarchy in modern processors is based on: (7 points)

    • Avoid conflicts between cores or computing units
    • Ease the access load of DRAM memory
    • Accelerate data accesses by using SRAM memories close to the computing units
    • Increase the storage capacities by adding SRAM

  4. Order the memories according to the access speeds from a CPU: (14 points)

    • DRAM
    • L3
    • Registers
    • L2
    • Hard drive
    • L1

  5. Select which type of memory corresponds to each description: (14 points)

    Description SRAM DRAM
    Less expensive ☐ ☐
    Faster access ☐ ☐
    Uses more transistors ☐ ☐
    Requires refreshing memory ☐ ☐
    Is located closer to the processor ☐ ☐
    Also known as main memory ☐ ☐

  6. What coherence protocol was applied in the following scenario on a multi-core CPU? (7 points)

    In a quad core CPU there are 4 threads running independently in each of the cores. The task that threads perform is to update positions of a shared array in main memory. When a thread changes a value of a certain position of the array, immediately a process is in charge of updating all the copies of that position of the array in the caches of the other cores.

    • Snooping
    • Update
    • Invalidate

  7. Select the characteristics in common that Nvidia, AMD, and Intel GPUs have: (7 points)

    • Architecture based on many small cores (or computing units) clustered
    • Cores or computational units more complex than CPU
    • Can run hundreds or thousands of threads in parallel
    • Include cache-based memory hierarchy

  8. What can a programmer define in an FPGA? (7 points)

    • The size of its internal memory
    • The functionality of logic blocks
    • Establish interconnection routes between logic blocks
    • The number of transistors on the chip
    • Set the clock and reset